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1 features ? contains two echo cancellers: 112ms acoustic echo canceller + 16ms line echo canceller ? works with low cost voice codec. itu-t g.711 or signed mag m /a-law, or linear 2s comp ? each port may operate in different format. ? advanced nlp design - full duplex speech with no switched loss on audio paths ? fast re-convergence time: tracks changing echo environment quickly ? adaptation algorithm converges even during double-talk ? designed for exceptional performance in high background noise environments ? provides protection against narrow-band signal divergence ? howling prevention stops uncontrolled oscillation in high loop gain conditions ? offset nulling of all pcm channels ? serial micro-controller interface ? st-bus or variable-rate ssi pcm interfaces ? user gain control provided for speaker path (-24db to +21db in 3db steps) ? agc on speaker path ? handles up to 0 db acoustic echo return loss and 0db line erl ? transparent data transfer and mute options ? 20 mhz master clock operation ? low power mode during pcm bypass applications ? full duplex speaker-phone for digital telephone ? echo cancellation for video conferencing ? handsfree in automobile environment ? full duplex speaker-phone for pc figure 1 - functional block diagram rout md1 md2 port 2 sin line echo path s 1 ds5038 issue 3 february 1999 ordering information MT9315ap 28 pin plcc MT9315ae 28 pin pdip -40 c to + 85 c cmos MT9315 acoustic echo canceller advance information format l inear/ m /a-law offset null linear m /a-law/ linear/ m /a-law micro interface adaptive filter offset null vdd vss pwrdn f0i bclk/ c4i mclk sout rin data1 data2 cs sclk ena2 law agc user gain + - adv + - -24 -> +21db r 1 r 2 r 3 s 2 s 3 nlp adv nlp linear m /a-law/ + + howling controller port 1 nbsd adaptive filter unit control detector talk double nbsd ena1 limiter limiter acoustic echo path
MT9315 advance information 2 figure 2 - pin connections pin description pin # name description 1 ena1 ssi enable strobe / st-bus mode for rin/sout (input) . this pin has dual functions depending on whether ssi or st-bus is selected. for ssi, this strobe must be present for frame synchronization. this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial pcm data transfer for on rin/sout pins. strobe period is 125 microseconds. for st-bus, this pin, in conjunction with the md1 pin, will select the proper st-bus mode for rin/sout pins (see st-bus operation description). 2 md1 st-bus mode for rin/sout (input) . when in st-bus mode, this pin, in conjunction with the ena1 pin, will select the proper st-bus mode for rin/sout pins (see st-bus operation description). connect this pin to vss in ssi mode. 3 ena2 ssi enable strobe / st-bus mode for sin/rout (input) .this pin has dual functions depending on whether ssi or st-bus is selected. for ssi, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial pcm data transfer on sin/rout pins. strobe period is 125 microseconds. for st-bus, this pin, in conjunction with the md2 pin, will select the proper st-bus mode for sin/rout pins (see st-bus operation description). 4 md2 st-bus mode for sin/rout (input) .when in st-bus mode, this pin in conjunction with the ena2 pin, will select the proper st-bus mode for sin/rout pins (see st-bus operation description). connect this pin to vss in ssi mode. 5 rin receive pcm signal input (input). 128 kbit/s to 4096 kbit/s serial pcm input stream. data may be in either companded or 2s complement linear format. this is the receive input channel from the line (or line) side. data bits are clocked in following ssi or st-bus timing requirements. 6 sin send pcm signal input (input). 128 kbit/s to 4096 kbit/s serial pcm input stream. data may be in either companded or 2s complement linear format. this is the send input channel (from the microphone). data bits are clocked in following ssi or st-bus timing requirements. 7 vss digital ground: nominally 0 volt. 8 mclk master clock (input): nominal 20 mhz master clock input. may be connected to an asynchronous (relative to frame signal) clock source. 9ic internal connection (input): must be tied to vss. 10, 11 ic internal connection (input). tie to vss. 12 law a/ m law select (input). when low, selects m- law companded pcm. when high, selects a- law companded pcm. this control is for both serial pcm ports. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 data2 vdd nc ic nc data1 sclk sout rout bclk/ c4i ic ic sin rin ic vss md2 md1 f0i format ic law ena1 pwrdn nc ena2 mclk cs md2 md1 ena1 ena2 bclk/ c4i ic ic ic sin rin ic vss ic mclk format law pwrdn nc nc sclk cs data2 vdd nc data1 sout rout f0i plcc 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 3 2 1 28 27 26 12 13 14 15 16 17 18 pdip
advance information MT9315 3 notes: 1. all inputs have ttl compatible logic levels except for mclk, sin and rin pins which have cmos compatible logic levels and pwrdn pin which has schmitt trigger compatible logic levels. 2. all outputs are cmos pins with cmos logic levels except data1 which is ttl bidirectional. glossary double-talk simultaneous signals present on rin and sin. near-end single-talk signals only present at sin input. far-end single-talk signals only present at rin input. adv nlp advanced non-linear-processor howling oscillation caused by feedback from acoustic and line echo paths narrowband any mono or dual sinusoidal signals nbsd narrow band signal detector noise-gating audible switching of background noise offset nulling removal of dc component reverberation time the time duration before an echo level decays to -60dbm erl echo return loss erle echo return loss enhancement agc automatic gain control 13 format itu-t/ sign ma g (input). when low, selects sign-magnitude pcm code. when high, selects itu-t (g.711) pcm code. this control is for both serial pcm ports. 14 pwrdn power-down (input). an active low resets the device and puts the MT9315 into a low-power stand-by mode. 15, 16 nc no connect (output). this pin should be left un-connected. 17 sclk serial port synchronous clock (input). data clock for the serial microport interface. 18 cs serial port chip select (input). enables serial microport interface data transfers. active low. 1 9 data 2 serial data receive (input). in motorola/national serial microport operation, the data2 pin is used for receiving data. in intel serial microport operation, the data2 pin is not used and must be tied to vss or vdd. 2 0 data 1 serial data port (bidirectional). in motorola/national serial microport operation, the data1 pin is used for transmitting data. in intel serial microport operation, the data1 pin is used for transmitting and receiving data. 21 nc no connect (output). this pin should be left un-connected. 22 vdd positive power supply. nominal is 5v 23 sout send pcm signal output (output). 128 kbit/s to 4096 kbit/s serial pcm output stream. data may be in either companded or 2s complement linear pcm format. this is the send out signal after acoustic echo cancellation and non-linear processing. data bits are clocked out following ssi or st-bus timing requirements. 24 rout receive pcm signal output (output). 128 kbit/s to 4096 kbit/s serial pcm output stream. data may be in either companded or 2s complement linear pcm format. this is the receive out signal after line echo cancellation non-linear processing, agc, and gain control. data bits are clocked out following ssi or st-bus timing requirements. 25 f0i frame pulse (input). in st-bus operation, this is an active-low frame alignment pulse. ssi operation is enabled by connecting this pin to vss. 26 bclk/ c4i bit clock/st-bus clock (input) . in ssi operation, bclk pin is a 128 khz to 4.096 mhz bit clock. this clock must be synchronous with ena1, and ena2 enable strobes. in st-bus operation, c4i pin must be connected to the 4.096mhz ( c4) system clock. 27, 28 ic internal connection (input). tie to vss. pin description (continued) pin # name description
MT9315 advance information 4 functional description the MT9315 device contains two echo cancellers, as well as the many control functions necessary to operate the echo cancellers. one canceller is for acoustic speaker to microphone echo, and one for line echo cancellation. the MT9315 provides clear signal transmission in both audio path directions to ensure reliable voice communication, even with low level signals. the MT9315 does not use variable attenuators during double-talk or single-talk periods of speech, as do many other acoustic echo cancellers for speaker-phones. instead, the MT9315 provides high performance full-duplex operation similar to network echo cancellers, so that users experience clear speech and un-interrupted background signals during the conversation. this prevents subjective sound quality problems associated with noise gating or noise contrasting. the MT9315 uses an advanced adaptive ?lter algorithm that is double-talk stable, which means that convergence takes place even while both parties are talking 1 . this algorithm allows continual tracking of changes in the echo path, regardless of double- talk, as long as a reference signal is available for the echo canceller. (1. patent pending) the echo tail cancellation capability of the acoustic echo canceller has been sized appropriately (112ms) to cancel echo in an average sized of?ce with a reverberation time of less than 112ms. the 16ms line echo canceller is suf?cient to ensure a high erle for most line circuits. in addition to the echo cancellers, the following functions are supported: ? control of adaptive ?lter convergence speed during periods of double-talk, far end single- talk, and near-end echo path changes. ? control of non-linear processor thresholds for suppression of residual non-linear echo. ? howling detector to identify when instability is starting to occur, and to take action to prevent oscillation. ? narrow-band detector for preventing adaptive ?lter divergence caused by narrow-band signals ? offset nulling ?lters for removal of dc components in pcm channels. ? limiters that introduce controlled saturation levels. ? serial controller interface compatible with motorola, national and intel microcontrollers. ? pcm encoder/decoder compatible with m /a- law itu-t g.711, m /a-law sign-mag or linear 2s complement coding. ? automatic gain control on the receive speaker path. adaptation speed control the adaptation speed of the acoustic echo canceller is designed to optimize the convergence speed versus divergence caused by interfering near-end signals. adaptation speed algorithm takes into account many different factors such as relative double-talk condition, far end signal power, echo path change, and noise levels to achieve fast convergence. advanced non-linear processor (adv-nlp) 2 (2. patent pending) after echo cancellation, there is likely to be residual echo which needs to be removed so that it will not be audible. the MT9315 uses an nlp to remove low level residual echo signals which are not comprised of background noise. the operation of the nlp depends upon a dynamic activation threshold, as well as a double-talk detector which disables the nlp during double-talk periods. the MT9315 keeps the perceived noise level constant, without the need for any variable attenuators or gain switching that causes audible noise gating. the noise level is constant and identical to the original background noise even when the nlp is activated. for each audio path, the nlp can be disabled by setting the nlp- bit to 1 in the lec or aec control registers. narrow band signal detector (nbsd) 3 (3. patent pending) single or multi-frequency tones (e.g. dtmf, or signalling tones) present in the reference input of an echo canceller for a prolonged period of time may cause the adaptive ?lter to diverge. the narrow band signal detector (nbsd) is designed to prevent this divergence by detecting single or multi-tones of arbitrary frequency, phase, and amplitude. when narrow band signals are detected, the ?lter adaptation process is stopped but the echo canceller continues to cancel echo. the nbsd can be disabled by setting the nb- bit to 1 in the mc control registers.
advance information MT9315 5 howling detector (hwld) 4 (4. patent pending) the howling detector is part of an anti-howling control, designed to prevent oscillation as a result of positive feedback in the audio paths. the hwld can be disabled by setting the ah- bit to 1 in the (mc) control register. offset null filter to ensure robust performance of the adaptive ?lters at all times, any dc offset that may be present on either the rin signal or the sin signal, is removed by highpass ?lters. these ?lters have a corner frequency placed at 40hz. the offset null ?lters can be disabled by setting the hpf- bit to 1 in the lec or aec control registers. limiters to prevent clipping in the echo paths, two limiters with variable thresholds are provided at the outputs. the rout limiter threshold is in rout limiter register 1 and 2. the sout limiter threshold is in sout limiter register. both output limiters are always enabled. user gain the user gain function provides the ability for users to adjust the audio gain in the receive path (speaker path). this gain is adjustable from -24db to +21db in 3db steps. it is important to use only this user gain function to adjust the speaker volume. the user gain function in the MT9315 is optimally placed between the two echo cancellers such that no reconvergence is necessary after gain changes. the gain can be accessed through receive gain control register. agc the agc function is provided to limit the volume in the speaker path. the gain of the speaker path is automatically reduced during the following conditions: ? when clipping of the receive signal occurs. ? when initial convergence of the acoustic echo canceller detects unusually large echo return. ? when howling is detected. the agc can be disabled by setting the agc- bit to 1 in mc control register. mute function a pcm mute function is provided for independent control of the receive and send audio paths. setting the mute_r or mute_s bit in the mc register, causes quiet code to be transmitted on the rout or sout paths respectively. quiet code is de?ned according to the following table. bypass control a pcm bypass function is provided to allow transparent transmission of pcm data through the MT9315. when the bypass function is active, pcm data passes transparently from rin to rout and from sin to sout, with bit-wise integrity preserved. when the bypass function is selected, most internal functions are powered down to provide low power consumption. the bypass control bit is located in the main control mc register. adaptation enable/disable adaptation control bits are located in the aec and lec control registers. when the adapt- bit is set to 1, the adaptive ?lter is frozen at the current state. in this state, the device continues to cancel echo with the current echo model. when the adapt- bit is set to 0, the adaptive ?lter is continually updated. this allows the echo canceller to adapt and track changes in the echo path. this is the normal operating state. MT9315 throughput delay in all modes, voice channels always have 2 frames of delay. in st-bus operation, the d and c channels have a delay of one frame. linear 16 bits 2s complement sign/ magnitude m -law a-law ccitt (g.711) m -law a-law +zero (quiet code) 0000h 80h ffh d5h table 1 - quiet pcm code assignment
MT9315 advance information 6 power down forcing the pwrdn pin to logic low, will put the MT9315 into a power down state. in this state all internal clocks are halted, the data1, sout and rout pins are tristated. the user should hold the pwrdn pin low for 200 msec on power-up. this will insure that the device powers up in a proper state. the device will automatically begin the execution of initialization routines when the pwrdn pin is returned to logic high and a clock is applied to the mclk pin. the initialization routines execute for one frame and will set the MT9315 to default register values. after power down, the user waits for 2 complete 8 khz frames prior to writing to the device registers. pcm data i/o the pcm data transfer for the MT9315 is provided through two pcm ports. one port consists of rin and sout pins while the second port consists of sin and rout pins. the data are transferred through these ports according to either st-bus or ssi conventions. the device determines the convention by monitoring the signal applied to the f0i pin. when a valid st- bus frame pulse is applied to the f0i pin, the MT9315 will assume st-bus operation. if f0i is tied continuously to vss, the MT9315 will assume ssi operation. st-bus operation the st-bus pcm interface conforms to mitels st- bus standard and it is used to transport 8 bit companded pcm data (using one timeslot) or 16 bit 2s complement linear pcm data (using two timeslots). the md1/ena1 pins select the timeslot on the rin/sout port while the md2/ena2 pin selects the timeslot on the sin/rout port. see table 2 and figures 3 to 6. table 2 - st-bus mode select ssi operation the ssi pcm interface consists of data input pins (rin, sin), data output pins (sout, rout), a variable rate bit clock (bclk), and two enable pins (ena1, ena2) to provide strobes for data transfers. the active high enable may be either 8 or 16 bclk cycles in duration. automatic detection of the data type (8 bit companded or 16 bit 2s complement linear) is accomplished internally. the data type cannot change dynamically from one frame to the next. in ssi operation, the frame boundary is determined by the rising edge of the ena1 enable strobe (see figure 7). the other enable strobe (ena2) is used for parsing input/output data and it must pulse within 125 microseconds of the rising edge of ena1. in ssi operation, the enable strobes may be a mixed combination of 8 or 16 bclk cycles allowing the ?exibility to mix 2s complement linear data on one port (e.g., rin/sout) with companded data on the other port (e.g., sin/rout). table 3 - ssi enable strobe pins pcm law and format control (law, format) the pcm companding/coding law used by the MT9315 is controlled through the law and format pins. itu-t g.711 companding curves for m -law and a-law are selected by the law pin. pcm coding itu-t g.711 and sign-magnitude are selected by the format pin. see table 4. port1 rin/sout st-bus mode selection port2 sin/rout enable pins enable pins md1 ena1 md2 ena2 00 mode 1. 8 bit companded pcm i/o on timeslot 0 00 01 mode 2. 8 bit companded pcm i/o on timeslot 2. 01 10 mode 3. 8 bit companded pcm i/o on timeslot 2. includes d & c channel bypass in timeslots 0 & 1. 10 11 mode 4. 16 bit 2s complement linear pcm i/o on timeslots 0 & 1. 11 enable strobe pin designated pcm i/o port ena1 line side echo path (port 1) ena2 acoustic side echo path (port 2)
advance information MT9315 7 linear pcm the 16-bit 2s complement pcm linear coding permits a dynamic range beyond that which is speci?ed in itu-t g.711 for companded pcm. the echo-cancellation algorithm will accept 16 bits 2s complement linear code which gives a maximum signal level of +15dbm0. bit clock (bclk/ c4i) the bclk/ c4i pin is used to clock the pcm data in both ssi (bclk) and st-bus ( c4i) operations. in ssi operation, the bit rate is determined by the bclk frequency. this input must contain either eight or sixteen clock cycles within the valid enable strobe window. bclk may be any rate between 128 khz to 4.096 mhz and can be discontinuous outside of the enable strobe windows de?ned by ena1, ena2 pins. incoming pcm data (rin, sin) are sampled on the falling edge of bclk while outgoing pcm data (sout, rout) are clocked out on the rising edge of bclk. see figure 11. in st-bus operation, connect the system c4 (4.096mhz) clock to the c4i pin. master clock (mclk) a nominal 20mhz master clock (mclk) is required. the mclk input may be asynchronous with the 8khz frame. microport the serial microport provides access to all MT9315 internal read and write registers. this microport is compatible with intel mcs-51 (mode 0), motorola spi (cpol=0, cpha=0), and national semiconductor microwire speci?cations. the microport consists of a transmit/receive data pin (data1), a receive data pin (data2), a chip select pin ( cs) and a synchronous data clock pin (sclk). the MT9315 automatically adjusts its internal timing and pin con?guration to conform to intel or motorola/ national requirements. the microport dynamically senses the state of the sclk pin each time cs pin becomes active (i.e. high to low transition). if sclk pin is high during cs activation, then intel mode 0 timing is assumed. in this case data1 pin is de?ned as a bi-directional (transmit/receive) serial port and data2 is internally disconnected. if sclk is low during cs activation, then motorola/national timing is assumed and data1 is de?ned as the data transmit pin while data2 becomes the data receive pin. the MT9315 supports motorola half-duplex processor mode (cpol=0 and cpha=0). this means that during a write to the MT9315, by the motorola processor, output data from the data1 pin must be ignored. this also means that input data on the data2 pin is ignored by the MT9315 during a valid read by the motorola processor. all data transfers through the microport are two bytes long. this requires the transmission of a command/ address byte followed by the data byte to be written to or read from the addressed register. cs must remain low for the duration of this two-byte transfer. as shown in figures 8 and 9, the falling edge of cs indicates to the MT9315 that a microport transfer is about to begin. the ?rst 8 clock cycles of sclk after the falling edge of cs are always used to receive the command/address byte from the microcontroller. the command/address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. the next 8 clock cycles are used to transfer the data byte between the MT9315 and the microcontroller. at the end of the two-byte transfer, cs is brought high again to terminate the session. the rising edge of cs will tri-state the data1 pin. the data1 pin will remain tri- stated as long as cs is high. intel processors utilize least signi?cant bit (lsb) ?rst transmission while motorola/national processors use most signi?cant bit (msb) ?rst transmission. the MT9315 microport automatically accommodates these two schemes for normal data bytes. however, to ensure timely decoding of the r/ w and address information, the command/address byte is de?ned differently for intel and motorola/national operations. refer to the relative timing diagrams of figure 8 and figure 9. receive data bits are sampled on the rising edge of sclk while transmit data is clocked out on the falling edge of sclk. detailed microport timing is shown in figure 13 and figure 14. pcm code sign-magnitude format=0 itu-t (g.711) format=1 m /a-law law = 0 or 1 m -law law = 0 a-law law =1 + full scale 1111 1111 1000 0000 1010 1010 + zero 1000 0000 1111 1111 1101 0101 - zero 0000 0000 0111 1111 0101 0101 - full scale 0111 1111 0000 0000 0010 1010 table 4 - companded pcm
MT9315 advance information 8 figure 3 - st-bus 8 bit companded pcm i/o on timeslot 0 (mode 1) figure 4 - st-bus 8 bit companded pcm i/o on timeslot 2 (mode 2) c4i f0i sin rout rin sout 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 outputs = high impedance inputs = dont care in st-bus mode 1, echo canceller i/o channels are assigned to st-bus timeslot 0. note that the user could con?gure port1 and port2 into different st-bus modes. port1 port2 01 2 34 b c4i f0i sin rout rin sout 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 in st-bus mode 2, echo canceller i/o channels are assigned to st-bus timeslot 2. note that the user could con?gure port1 and port2 into different st-bus modes. port1 port2 01 2 34 outputs = high impedance inputs = dont care b
advance information MT9315 9 figure 5 - st-bus 8 bit companded pcm i/o with d and c channels (mode 3) figure 6 - st-bus 16 bit 2s complement linear pcm i/o (mode 4) c4i f0i rin sout eca sin rout eca port1 port2 indicates that an input channel is bypassed to an output channel st-bus mode 3 supports connection to 2b+d devices where timeslots 0 and 1 transport d and c channels and echo canceller i/o channels are assigned to st-bus timeslot 2. both port1 and port2 must be con?gured in st-bus mode 3. 01 2 34 outputs = high impedance inputs = dont care 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 7654 3 21 0 d c b c4i f0i rin sout 76543210 sin rout port1 port2 s 14 13 12 11 10 9 8 st-bus mode 4 allows 16 bit 2s complement linear data to be transferred using st-bus i/o timing. note that port1 and port2 need not necessarily both be in mode 4. outputs = high impedance inputs = dont care 76543210 s 14 13 12 11 10 9 8 76543210 s 14 13 12 11 10 9 8 76543210 s 14 13 12 11 10 9 8
MT9315 advance information 10 figure 7 - ssi operation figure 8 - serial microport timing for intel mode 0 bclk ena1 rin sout 8 or 16 bits 8 or 16 bits port1 port2 8 or 16 bits 8 or 16 bits ena2 sin rout note that the two ports are independent so that, for example, port1 can operate with 8 bit enable strobes and port2 can operate with 16 bit enable strobes. outputs = high impedance inputs = dont care r/w a 0 a 1 a 2 a 3 a 4 a 5 x command/address data input/output data 1 sclk cs a ? ? a ? ? this delay is due to internal processor timing and is equal to tsch time. the delay is transparent to MT9315. the MT9315: outputs transmit data on the falling edge of sclk the falling edge of cs indicates that a command/address byte will be transmitted from the microprocessor. the subsequent byte is always data followed by cs returning high. a new command/address byte may be loaded only by cs cycling high then low again. the command/address byte contains: 1 bit - read/ wr ite 6 bits - addressing data 1 bit - unused d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 latches receive data on the rising edge of sclk
advance information MT9315 11 figure 9 - serial microport timing for motorola mode 00 or national microwire x a 0 a 1 a 2 a 3 a 4 a 5 r/w command/address data input data 2 receive data 1 transmit sclk cs a ? ? a ? ? this delay is due to internal processor timing and is equal to tsch time. the delay is transparent to MT9315. the falling edge of cs indicates that a command/address byte will be transmitted from the microprocessor. the subsequent byte is always data followed by cs returning high. a new command/address byte may be loaded only by cs cycling high then low again. the command/address byte contains: 1 bit - read/ wr ite 6 bits - addressing data 1 bit - unused d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 high impedance data output the MT9315: outputs transmit data on the falling edge of sclk latches receive data on the rising edge of sclk
MT9315 advance information 12 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. . absolute maximum ratings* parameter symbol min max units 1 supply voltage v dd -v ss -0.3 7.0 v 2 input voltage v i v ss -0.3 v dd + 0.3 v 3 output voltage swing v o v ss -0.3 v dd + 0.3 v 4 continuous current on any digital pin i i/o 20 ma 5 storage temperature t st -65 150 c 6 package power dissipation p d (5v) 500 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated characteristics sym min typ max units test conditions 1 supply voltage v dd 4.5 5.0 5.5 v 2 ttl input high voltage 2.4 v dd v 3 ttl input low voltage v ss 0.4 v 4 cmos input high voltage 2.1 v dd v 5 cmos input low voltage v ss 0.5 v 6 operating temperature t a -40 +85 c echo return limits - characteristics min typ max units test conditions 1 acoustic echo return 0 db measured from rout -> sin 2 line echo return 0 db measured from sout -> rin dc electrical characteristics* - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units conditions/notes 1 standby supply current: i cc 60 m a pwrdn = 0 operating supply current: i dd 50 ma pwrdn = 1, clocks active 2 input high voltage (ttl) v ih 2.0 v all except mclk,sin,rin 3 input low voltage (ttl) v il 0.8 v all except mclk,sin,rin 4 input high voltage (cmos) v ihc 0.7v dd v mclk,sin,rin 5 input low voltage (cmos) v ilc 0.3v dd v mclk,sin,rin 6 input leakage current i ih /i il 0.1 10 m av in =v ss to v dd 7 high level output voltage v oh 0.9 v dd vi oh =2.5ma 8 low level output voltage v ol 0.1v dd vi ol =5.0ma 9 high impedance leakage i oz 110 m av in =v ss to v dd 10 output capacitance c o 10 pf
advance information MT9315 13 ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. *dc electrical characteristics are over recommended temperature and supply voltage. ? timing is over recommended temperature and power supply voltages. 11 input capacitance c i 8pf 12 pwrdn positive threshold voltage hysteresis negative threshold voltage v+ v h v- 0.75 v dd 1.0 0.25 v dd v v v ac electrical characteristics ? - serial data interfaces - voltages are with respect to ground (v ss ) unless otherwise stated characteristics sym min typ max units test notes 1 mclk clock high t mch 20 ns 2 mclk clock low t mcl 20 ns 3 mclk frequency f clk 19.15 20.5 mhz 4 bclk/ c4i clock high t bch, t c4h 90 ns 5 bclk/ c4i clock low t bll, t c4l 90 ns 6 bclk/ c4i period t bcp 240 7900 ns 7 ssi enable strobe to data delay (?rst bit) t sd 80 ns c l =150pf 8 ssi data output delay (excluding ?rst bit) t dd 80 ns c l =150pf 9 ssi output active to high impedance t ahz 80 ns c l =150pf 10 ssi enable strobe signal setup t sss 10 t bcp -15 ns 11 ssi enable strobe signal hold t ssh 15 t bcp -10 ns 12 ssi data input setup t dis 10 ns 13 ssi data input hold t dih 15 ns 14 f0i setup t f0is 20 150 ns 15 f0i hold t f0ih 20 150 ns 16 st-bus data output delay t dsd 80 ns c l =150pf 17 st-bus output active to high impedance t ashz 80 ns c l =150pf 18 st-bus data input hold time t dsh 20 ns 19 st-bus data input setup time t dss 20 ns dc electrical characteristics* - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units conditions/notes
MT9315 advance information 14 ? timing is over recommended temperature range and recommended power supply voltages. table 8 - reference level de?nition for timing measurements figure 10 - master clock - mclk notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol de?nitions) ac electrical characteristics ? - microport timing characteristics sym min typ max units test notes 1 input data setup t ids 100 ns 2 input data hold t idh 30 ns 3 output data delay t odd 100 ns c l =150pf 4 serial clock period t scp 500 ns 5 sclk pulse width high t sch 250 ns 6 sclk pulse width low t scl 250 ns 7 cs setup-intel t cssi 200 ns 8 cs setup-motorola t cssm 100 ns 9 cs hold t csh 100 ns 10 cs to output high impedance t ohz 100 ns c l =150pf characteristic symbol ttl pin cmos pin units ttl reference level v tt 1.5 - v cmos reference level v ct - 0.5*v dd v input high level v h 2.4 0.9*v dd v input low level v l 0.4 0.1*v dd v rise/fall high measurement point v hm 2.0 0.7*v dd v rise/fall low measurement point v hl 0.8 0.3*v dd v mclk (3) v h v l v ct t mcl t mch
advance information MT9315 15 figure 11 - ssi data port timing notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol de?nitions) figure 12 - st-bus data port timing notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol de?nitions) sout/rout (1) v ct bclk (2) v h v l v tt ena1/ena2 (2) v h v l v tt rin/sin (3) v h v l v ct t sd t sss t dd t ahz t ssh t dis t dih t bcp t bch t bcl bit 0 bit 1 bit 0 bit 1 or enb1/enb2 (2) sout/rout (1) v ct c4i (2) v h v l v tt f0i (2) v h v l v tt rin/sin (3) v h v l v ct t f0is t f0ih t dss t dsh t dsd t ashz t c4h t c4l bit 0 bit 1 bit 0 bit 1
MT9315 advance information 16 figure 13 - intel serial microport timing notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol de?nitions) figure 14 - motorola serial microport timing notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol de?nitions) data1 (1, 2) v tt ,v ct sclk (2) v h v l v tt cs ( 2) v h v l v tt t ids t idh t odd t ohz t cssi t csh t scl t sch t scp data input data output data2 (2) v h v l v tt sclk (2) v h v l v tt cs (2) v h v l v tt data1 (1) v ct t ids t idh t odd t cssm t csh t ohz t sch t scl t scp (input) (output)
advance information MT9315 17 register summary address: 00h r/w main control register (mc) power up reset 00h reset when high, the power initialization routine is executed presetting all registers to default values. this bit automatically clears itself to0 when reset is complete. ah- when high, the howling detector is disabled and when low the howling detector is enabled. agc- when high, agc is disabled and when low agc is enabled nb- when high, narrowband signal detectors in rin and sin paths are disabled and when low the signal detectors are enabled bypass when high, the send and receive paths are transparently by-passed from input to output and when low the send and receive paths are not bypassed mute_s when high, the sin path is muted to quite code (after the nlp) and when low the sin path is not muted mute_r when high, the rin path is muted to quite code (after the nlp) and when low the rin path is not muted limit when high, the 2-bit shift mode is enabled in conjunction with bit 7 of lec register and when low 2-bit shift mode is disabled address: 21h r/w acoustic echo canceller control register (aec) power up reset 00h ecby when high, the echo estimate from the ?lter is not substracted from the send path, when low the estimate is substracted adapt- when high, the echo canceller adaptation is disabled and when low the adaptation is enabled hclr when high, adaptive ?lter coef?cients are cleared and when low the ?lter coef?cients are not cleared hpf- when high, offset nulling ?lter is bypassed in the sin/sout path and when low the offset nulling ?lter in not bypassed inj- when high, the noise ?ltering process is disabled in the nlp and when low the noise ?ltering process is enabled nlp- when high, the non linear processor is disabled in the sin/sout path and when low the nlp is enabled asc- when high, the internal adaptation speed control is disabled and when low the adaptation speed is enabled p- when high, the exponential weighting function for the adaptive ?lter is disabled and when low the weighting function is enabled address: 01h r/w line echo canceller control register (lec) power up reset 00h ecby when high, the echo estimate from the ?lter is not substracted from the send path, when low the estimate is substracted adapt- when high, the echo canceller adaptation is disabled and when low the adaptation is enabled hclr when high, adaptive ?lter coef?cients are cleared and when low the ?lter coef?cients are not cleared hpf- when high, offset nulling ?lter is bypassed in the rin/rout path and when low the offset nulling ?lter in not bypassed inj- when high, the noise ?ltering process is disabled in the nlp and when low the noise ?ltering process is enabled nlp- when high, the non linear processor is disabled in the rin/rout path and when low the nlp is enabled asc- when high, the internal adaptation speed control is disabled and when low the adaptation speed is enabled shft when high the 16-bit linear mode, inputs sin, rin, are shift right by 2 and outputs sout, rout are shift left by 2. this bit is ignored when 16-bit linear mode is not selected in both ports. this bit is also ignored if bit 7 of mc register is set to zero 76 5 0 43 1 2 limit mute_r mute_s bypass nb- agc- ah- reset lsb msb 76 5 0 43 1 2 p- asc- nlp- inj- hpf- hclr adapt- ecby lsb msb 76 5 0 43 1 2 shft asc- nlp- inj- hpf- hclr adapt- ecby lsb msb
MT9315 advance information 18 gain values for receive gain control register bit g3 to g0 (rgc) address: 22h read acoustic echo canceller status register (asr) ( * do not write to this register ) power up reset 00h nbs when high, the narrowband signal has been detected in the sin/sout path and when low, the narrowband signal has not been detected in the sin/sout path nb logical or of the status bit nbs + nbr from lsr register dt when high the double talk is detected and when low, the double talk is not detected nlpdc when high, the nlp is activated and when low the nlp is not activated - reserved. hwlng when high, howling is occurring in the loop and when low, no howling is detected acmund when high, no active signal in the rin/rout path - reserved. address: 02h read line echo canceller status register (lsr) ( * do not write to this register ) power up reset 00h nbr when high, a narrowband signal has been detected in the receive (rin) path. when low no narrowband signal is not detected in the rin path nb this bit indicates a logical-or of stattus bits nbr + nbs ( from asr register) dt when high, double-talk is detected and when low double-talk is not detected nlpc when high, nlp is actiivated and when low nlp is not activated - reserved. . - - -- address: 20h r/w receive gain control register (rgc) power up reset 6dh g0 user gain control on the rin/rout path (tolerance of gains: +/- 0.15 db). the hexadecimal number represents g3 to g0 value in the table below. g1 g2 g3 - reserved - - - 0h -24db 4h -12db 8h 0 db ch +12 db 1h -21db 5h -9 db 9h + 3 db dh + 15 db 2h -18db 6h -6 db ah + 6 db eh + 18 db 3h -15db 7h -3 db bh +9 db fh + 21 db 76 5 0 43 1 2 - acmund hwlng - nlpdc dt nb nbs lsb msb 76 5 0 43 1 2 lsb msb - go g1 g2 g3 - - - 7 65 0 43 1 2 lsb msb - nbr nb dt nlpc - - -
advance information MT9315 19 address: 16h read receive (rin) peak detect register 1 (ripd1) power up reset 00h ripd 0 these peak detector registers allow the user to monitor the receive in signal (rin) peak level at reference point r1 (see figure #1). the information is in 16-bit 2s complement linear coded format presented in two 8 bit registers. the high byte is in register 2 and the low byte is in register 1. ripd 1 ripd 2 ripd 3 ripd 4 ripd 5 ripd 6 ripd 7 address: 17h read receive (rin) peak detect register 2 (ripd2) power up reset 00h ripd 8 see above description ripd 9 ripd 10 ripd 11 ripd 12 ripd 13 ripd 14 ripd 15 address: 18h read receive (rin) error peak detect register 1 (repd1) power up reset 00h repd 0 these peak detector registers allow the user to monitor the error signal peak level at reference point r2 (see figure #1). the information is in 16-bit 2s complement linear coded format presented in two 8 bit registers. the high byte is in register 2 and the low byte is in register 1. repd 1 repd 2 repd 3 repd 4 repd 5 repd 6 repd 7 76 5 0 43 1 2 ripd 7 lsb msb ripd 6 ripd 5 ripd 4 ripd 3 ripd 2 ripd 1 ripd 0 76 5 0 43 1 2 ripd 15 lsb msb ripd 14 ripd 13 ripd 12 ripd 11 ripd 10 ripd 9 ripd 8 76 5 0 43 1 2 repd 7 lsb msb repd 6 repd 5 repd 4 repd 3 repd 2 repd 1 repd 0
MT9315 advance information 20 address: 19h read receive (rin) error peak detect register 2 (repd2) power up reset 00h repd8 see above description repd9 repd10 repd11 repd12 repd13 repd14 repd15 address: 3ah read receive (rout) peak detect register 1 (ropd1) power up reset 00h ropd 0 these peak detector registers allow the user to monitor the receive out signal (rout) peak level at reference point r3 (see figure #1). the information is in 16-bit 2s complement linear coded format presented in two 8 bit registers. the high byte is in register 2 and the low byte is in register 1. ropd 1 ropd 2 ropd 3 ropd 4 ropd 5 ropd 6 ropd 7 address: 3bh read receive (rout) peak detect register 2 (ropd2) power up reset 00h ropd 8 see above description ropd 9 ropd 10 ropd 11 ropd 12 ropd 13 ropd 14 ropd 15 76 5 0 43 1 2 ropd 15 lsb msb ropd 14 ropd 13 ropd 12 ropd 10 ropd 9 ropd 8 76 5 0 43 1 2 ropd 7 lsb msb ropd 6 ropd 5 ropd 4 ropd 3 ropd 2 ropd 1 ropd 0 ropd 11 76 5 0 43 1 2 repd 15 lsb msb repd 14 repd 13 repd 12 repd 10 repd 9 repd 8 repd 11
advance information MT9315 21 address: 36h read send (sin) peak detect register 1 (sipd1) power up reset 00h sipd 0 these peak detector registers allow the user to monitor the receive in signal (sin) peak level at reference point s1 (see figure #1). the information is in 16-bit 2s complement linear coded format presented in two 8 bit registers. the high byte is in register 2 and the low byte is in register 1. sipd 1 sipd 2 sipd 3 sipd 4 sipd 5 sipd 6 sipd 7 address: 37h read send (sin) peak detect register 2 (sipd2) power up reset 00h sipd 8 see above description sipd 9 sipd 10 sipd 11 sipd 12 sipd 13 sipd 14 sipd 15 address: 38h read send error peak detect register 1 (sepd1) power up reset 00h sepd 0 these peak detector registers allow the user to monitor the error signal peak level in the send path at reference point s2 (see figure #1). the information is in 16-bit 2s complement linear coded format presented in two 8 bit registers. the high byte is in register 2 and the low byte is in register 1. sepd 1 sepd 2 sepd 3 sepd 4 sepd 5 sepd 6 sepd 7 76 5 0 43 1 2 sipd 7 lsb msb sipd 6 sipd 5 sipd 4 sipd 3 sipd 2 sipd 1 sipd 0 76 5 0 43 1 2 sipd 15 lsb msb sipd 14 sipd 13 sipd 12 sipd 11 sipd 10 sipd 9 sipd 8 76 5 0 43 1 2 sepd 7 lsb msb sepd 6 sepd 5 sepd 4 sepd 3 sepd 2 sepd 1 sepd 0
MT9315 advance information 22 address: 39h read send error peak detect register 2 (sepd2) power up reset 00h sepd8 see above description sepd9 sepd10 sepd11 sepd12 sepd13 sepd14 sepd15 address: 1ah read send (sout) peak detect register 1 (sopd1) power up reset 00h sopd 0 these peak detector registers allow the user to monitor the send out signal (sout) peak level at reference point s3 (see figure #1). the information is in 16-bit 2s complement linear coded format presented in two 8 bit registers. the high byte is in register 2 and the low byte is in register 1. sopd 1 sopd 2 sopd 3 sopd 4 sopd 5 sopd 6 sopd 7 address: 1bh read send (sout) peak detect register 2 (sopd2) power up reset 00h sopd 8 see above description sopd 9 sopd 10 sopd 11 sopd 12 sopd 13 sopd 14 sopd 15 76 5 0 43 1 2 sepd 15 lsb msb sepd 14 sepd 13 sepd 12 sepd 10 sepd 9 sepd 8 sepd 11 76 5 0 43 1 2 sopd 7 lsb msb sopd 6 sopd 5 sopd 4 sopd 3 sopd 2 sopd 1 sopd 0 76 5 0 43 1 2 sopd 15 lsb msb sopd 14 sopd 13 sopd 12 sopd 10 sopd 9 sopd 8 sopd 11
advance information MT9315 23 address: 3ch r/w acoustic echo canceller adaptation speed register 1 (a_as1) power up reset 00h a_as 0 this register allows the user to program control the adaptation speed of the acoustic echo canceller. this register value changes dynamically when the asc- bit in the acoustic echo canceller control register is low. the asc- bit must be 1 when this register is under user control. the valid range is from 0000h to 7fffh. the high byte is in register 2 and the low byte is in register 1. smaller values correspond to slower adaptation speed. a_as 1 a_as 2 a_as 3 a_as 4 a_as 5 a_as 6 a_as 7 address: 3dh r/w acoustic echo canceller adaptation speed register 2 (a_as2) power up reset 10h a_as 8 see above description a_as 9 a_as 10 a_as 11 a_as 12 a_as 13 a_as 14 a_as 15 address: 1ch r/w line echo canceller adaptation speed register 1 (l_as1) power up reset 00h l_as 0 this register allows the user to program control the adaptation speed of the line echo canceller. this register value changes dynamically when the asc- bit in the acoustic echo canceller control register is low. the asc- bit must be 1 when this register is under user control. the valid range is from 0000h to 7fffh. the high byte is in register 2 and the low byte is in register 1. smaller values correspond to slower adaptation speed. l_as 1 l_as 2 l_as 3 l_as 4 l_as 5 l_as 6 l_as 7 76 5 0 43 1 2 a_as 7 lsb msb a_as 6 a_as 5 a_as 4 a_as 3 a_as 2 a_as 1 a_as 0 76 5 0 43 1 2 a_as 15 lsb msb a_as 14 a_as 13 a_as 12 a_as 10 a_as 9 a_as 8 a_as 11 76 5 0 43 1 2 l_as 7 lsb msb l_as 6 l_as 5 l_as 4 l_as 3 l_as 2 l_as 1 l_as 0
MT9315 advance information 24 address: 1dh r/w line echo canceller adaptation speed register 2 (l_as2) power up reset 08h l_as 8 see above description l_as 9 l_as 10 l_as 11 l_as 12 l_as 13 l_as 14 l_as 15 address: 24h r/w rout limiter register 1 (rl1) power up reset 80h - reserved - - - - - - l 0 this bit is used in conjunction with rout limiter register 2. (see description below.) address: 25h r/w rout limiter register 2 (rl2) power up reset 3eh l 1 in conjunction with bit 7 ( l 0 ) of the above (rl1) register, this register (rl2) allows the user to program the output limiter threshold value in the rout path. default value is (1f40)h which is equal to 3.14dbmo maximum value is (7fc0 )h = 15 dbmo minimum value is (0040)h = -38 dbmo l 2 l 3 l 4 l 5 l 6 l 7 l 8 76 5 0 43 1 2 l_as 15 lsb msb l_as 14 l_as 13 l_as 12 l_as 10 l_as 9 l_as 8 l_as 11 76 5 0 43 1 2 l 0 lsb msb - - - - - - - 76 5 0 43 1 2 l 8 lsb msb l 7 l 6 l 5 l 3 l 2 l 1 l 4
advance information MT9315 25 address: 26h r/w sout limiter register (sl) power up reset 3dh - reserved - - l 0 this register allows the user to program the output limiter threshold value in the rout path default value is (1f40)h which is equal to 3.14dbmo maximum value is (7f40 )h l 1 l 2 l 3 l 4 address: 03h read device revision code register (drc) power up reset 40h - reserved - - - drc 0 revision code of the device (=02). drc 1 drc 2 76 5 0 43 1 2 lsb msb - - - drc 2 drc 1 drc 0 - - 76 5 0 43 1 2 l 4 lsb msb l 3 l 2 l 1 l 0 - - -
package outlines plastic dual-in-line packages (pdip) - e suf?x note: controlling dimensions in parenthesis ( ) are in millimeters. dim 8-pin 16-pin 18-pin 20-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) a 2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) c 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) d 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) e 1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) l 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) e b 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) e c 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b e c general-8
package outlines plastic dual-in-line packages (pdip) - e suf?x dim 22-pin 24-pin 28-pin 40-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) a 2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) c 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) d 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) e 0.290 (7.37) .330 (8.38) e 1 0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 1 0.246 (6.25) 0.254 (6.45) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.400 bsc (10.16) 0.600 bsc (15.24) 0.600 bsc (15.24) 0.600 bsc (15.24) e a 0.300 bsc (7.62) e b 0.430 (10.92) l 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) a 15 15 15 15 e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b a shaded areas for 300 mil body width 24 pdip only
package outlines plastic j-lead chip carrier - p-suf?x f d 1 d h e 1 i a 1 a g d 2 e e 2 dim 20-pin 28-pin 44-pin 68-pin 84-pin min max min max min max min max min max a 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.200 (5.08) 0.165 (4.20) 0.200 (5.08) a 1 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.130 (3.30) 0.090 (2.29) 0.130 (3.30) d/e 0.385 (9.78) 0.395 (10.03) 0.485 (12.32) 0.495 (12.57) 0.685 (17.40) 0.695 (17.65) 0.985 (25.02) 0.995 (25.27) 1.185 (30.10) 1.195 (30.35) d 1 /e 1 0.350 (8.890) 0.356 (9.042) 0.450 (11.430) 0.456 (11.582) 0.650 (16.510) 0.656 (16.662) 0.950 (24.130) 0.958 (24.333) 1.150 (29.210) 1.158 (29.413) d 2 /e 2 0.290 (7.37) 0.330 (8.38) 0.390 (9.91) 0.430 (10.92) 0.590 (14.99) 0.630 (16.00) 0.890 (22.61) 0.930 (23.62) 1.090 (27.69) 1.130 (28.70) e 0 0.004 0 0.004 0 0.004 0 0.004 0 0.004 f 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) g 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) h 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) i 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) for d & e add for allowable mold protrusion 0.010" e: (lead coplanarity) general-10
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